Conventionally, exclusive control over shared data between different cores is important for shared memory multi-core processors. When data is shared among multiple cores and is processed without performing exclusive control, even if the cores execute the same process the same number of times, results may vary depending on the execution timing of the process. One technique of performing exclusive control has been disclosed as a technique of exclusive access to memory.
One example of exclusive access of memory is a method that uses an exclusive load command, an exclusive store command, and an exclusive access mechanism. This method expands the cores command set and bus protocol to enable the issue of special load/store commands on exclusive loading and exclusive storing. In addition, the exclusive access mechanism is disposed on a shared bus connecting multiple cores to shared memory. The exclusive access mechanism has a field recording therein identification information of a CPU that issues an exclusive load command and information of the address and the tag of a load destination, and monitors special load/store commands.
Exclusive access is defined as a state where exclusive storing is performed after exclusive loading is performed. An issuance of an exclusive access request is equivalent to exclusive loading having been performed, and completion of exclusive access is equivalent to exclusive storing having ended.
When an exclusive load command is issued, the exclusive access mechanism performs ordinary loading and returns data to the issuing CPU. The exclusive access mechanism records the address of the load destination. When searching information recorded in the exclusive access mechanism and finding no CPU having the same address as the recorded load destination and for which a tag is recorded in the exclusive access mechanism, the exclusive access mechanism records a tag for the exclusive load command issuing CPU.
When an exclusive store command is issued, if a recorded address associated with an issuing CPU matches the address of a storing destination and a tag is recorded, the exclusive access mechanism issues a store command, returns information indicating successful storage to the issuing CPU, and deletes tag information. Otherwise, the exclusive access mechanism does not issue a store command and executes an operation of returning to the issuing CPU, information indicating failed storage.
Utilization of exclusive loading and exclusive storing enables the matching of results regardless of the timing of processing. For example, when a given CPU performs exclusive loading and exclusive storing of a variable while another CPU performs exclusive loading of the same variable, if the other CPU performing exclusive loading later fails in exclusive storing, no result is reflected. As a result, the CPU having failed in exclusive storing executes the same process over again from exclusive loading, which allows the CPU to use a value properly reflecting the result of processing by the CPU having performed loading first. Hence, results can be matched regardless of timing of processing.
For example, a technique is disclosed, according to which the exclusive access mechanism is realized such that when an exclusive access request is made, a value representing execution of the request is recorded in a register, and when release from exclusive access occurs, the value is cleared from the register (see, e.g., Japanese Laid-Open Patent Publication No. H1-305457 indicated below).
As one method of realizing the exclusive access mechanism, another technique is disclosed, according to which when an exclusive access request is made, exclusive access is performed using information of a CPU ID, memory that is a device with an address to which the exclusive access request is made, I/O, etc. (see, e.g., Published Japanese-Translation of PCT Application, Publication No. 2007/099616 indicated below).
Still another technique is disclosed, according to which the exclusive access mechanism is realized by transmitting a release notification to each CPU when release from exclusive access occurs, and memory traffic is reduced by causing a CPU that has made an exclusive access request and failed to standby until the CPU receives release notification (see, e.g., Japanese Laid-Open Patent Publication No. H8-320828 indicated below).
In this manner, by using the exclusive access mechanism, data shared between different processors are processed properly. The exclusive access mechanism, however, can control an area of data of 32 bits or 64 bits at most, to which the exclusive access mechanism is accessible through one load/store command. OSs or application programs often share data in a larger area, because of which many OSs realize a function called spinlock by utilizing the exclusive access mechanism and thereby, realize exclusive control in a larger area. Overviews of spinlock are described, for example, in “Spinlock—Wikipedia, the free encyclopedia” [online], retrieved Apr. 9, 2010, Internet <URL:http://en.wikipedia.org/wiki/Spinlock> and “pthread spin_lock” [online], retrieved Apr. 9, 2010, Internet <URL:http://www.opengroup.org/onlinepubs/009695399/functions/pthread_spin_lock.htm>, and an example of spinlock is described, for example, in “User-Level Spin Locks—CodeProject” [online], retrieved Apr. 9, 2010, Internet <URL:http://www.codeproject.com/kb/threads/spinlocks.aspx>.
In the case of executing spinlock, a CPU additionally provided with a synchronization command and a synchronization wait command is present so that a CPU having failed in securing an area is caused to standby and is released from standby when becoming able to secure an area (see, e.g., “RealView Compilation Tools Version 3.1 Assembler Guide” [online], retrieved Apr. 9, 2010, Internet <URL:http://infocenter.arm.com/help/topic/com.arm.doc.dui0204h/DUI0204H_rvct_assembler_guide.pdf>, p. 4-139, p. 4-140 and “ARM11MPCore Processor Revision: r2p0 Technical Reference Manual” [online], retrieved Apr. 12, 2010, Internet <http://infocenter.arm.com/help/topic/com.arm.doc.ddi0360f/DDI0360F_arm11_mpcore_r2p0_trm.pdf>, p. 11-8). A synchronization command is a command to send a synchronous signal to a different CPU. A synchronization wait command is a command for a CPU to standby until receiving a synchronous signal. In application of this group of commands, a CPU having failed in securing an area issues a synchronization wait command and stands by, while a CPU having succeeded in securing an area sends a synchronous signal to a different CPU after ending exclusive storing. Hence, the CPU having failed in securing the area stands by to wait for a synchronous signal. As a result, access of a memory becomes less frequent, which enables a reduction in power consumption.
Among the above conventional techniques, however, the techniques of the exclusive access mechanism according to Patent documents 1 and 2 pose a problem in that because a synchronous signal is not sent at the timing of the completion of exclusive access, implementing a synchronization command and a synchronization wait command is difficult.
In the technique of the exclusive access mechanism according to Japanese Laid-Open Patent Publication No. H8-320828, a synchronization command and a synchronization wait command can be implemented because a synchronous signal is sent at the timing of the completion of exclusive access. A CPU to which the synchronous signal is to be sent is, however, not identified and thus, the synchronous signal is sent to each CPU. Consequently, a CPU in a standby state according to a synchronization wait command for a purpose other than exclusive access and a CPU having made an exclusive access request to a different area and being in a state of standby are released temporarily from the standby state and then are brought back into the standby state again. Hence, a problem of increased power consumption by CPUs arises.